The present invention relates to circuits, and more particularly, this invention relates to fractional-N PLL circuits and highly efficient development and/or optimization methods therefor.
The integrated circuit of a fractional-N phased-lock-loop (PLL) is widely used in communication systems. Such circuits feature high frequency resolution without degrading locking time. The conventional fractional-N PLL needs a long development time for meeting specifications for two main performance criteria: phase noise and spur. Any modification to the circuits normally leads to a very long manufacture time. For example, one tape out usually may take three months or more in manufacture time.
It would be desirable to obtain the maximum information on determining the phase noise source, minimizing the phase noise, and reducing the spurs. Furthermore, it would be desirable to find the phase noise sources and determine the main phase noise source because of the multiple phase noise sources in the system. One source of the phase noise is from the algorithm of a random number generator. Often, the random number generator uses an algorithm called MASH (multiple stage noise shaping) to shape the noise to a high frequency. A loop filter is then expected to filter out the noise.
In some cases, the random number generator may be a digital circuit which generates wide band noise which couples to the other part of the PLL through a power supply and substrate. Finding the actual source of the noise, however, is very difficult. There is thus a need for addressing these and/or other issues associated with the prior art.